Programmable resistance materials and fast switching materials are promising active materials for next-generation electronic storage, computing and signal transfer devices. A programmable resistance material possesses two or more states that differ in electrical resistance. The material can be programmed back and forth between the states by providing energy to the material to induce an internal transformation of the material that manifests itself as a change in resistance of the material. The different resistance states can be used to store or process data and the different resistance values of the resistance states can serve as identifying indicia of the states.
Fast switching materials are not based on programmable resistance change. They are, however, capable of being switched between a relatively resistive state, the quiescent low conduction state, and the highly conductive state. Application of an energy signal, typically an electrical energy signal, induces this change from the relatively resistive state to the relatively conductive state. The relatively conductive state persists for so long as the energy signal is applied. Once the energy signal is removed, the switching material relaxes back to its quiescent state. Devices that incorporate switching materials are useful as voltage clamping devices, surge suppression devices, signal routing devices, and access devices.
Phase change materials are a promising class of programmable resistance materials. A phase change material is a material that is capable of undergoing a transformation, preferably reversible, between two or more distinct structural states. In a common embodiment, a phase change material is reversibly transformable between a crystalline state and an amorphous state. In the crystalline state, the phase change material has low resistivity; while in the amorphous state, it has high resistivity. The distinct structural states of a phase change material may be distinguished on the basis of, for example, crystal structure, atomic arrangement, order or disorder, fractional crystallinity, relative proportions of two or more different structural states, a physical (e.g. electrical, optical, magnetic, mechanical) or chemical property etc. Reversibility of the transformations between structural states permits reuse of the material over multiple cycles of operation.
Typically, a programmable resistance material or switching device is formed by placing an active material, such as a phase change material, between two electrodes. Operation of the device is effected by providing an electrical signal between the two electrodes and across the active material. Programmable resistance materials may be used as the active material of a memory device. Write operations in a memory device, also called programming operations, which apply electric pulses to the memory device, and read operations, which measure the resistance of the memory device, are performed by providing current or voltage signals across the two electrodes. The transformation between the relative resistive state and relatively conductive state of a switching material is similarly induced by providing a current or voltage signal between two electrodes in contact with the switching material. One of the significant practical challenges that the programmable resistance memory and switching devices face is to reduce the contact area of one or more electrodes contacting the chalcogenide material. By reducing the contact area, the energy required to program a memory device or switch a switching device can be reduced and more efficient devices can be achieved.
Fabrication of semiconductor devices such as logic and memory devices typically includes a number of processes that may be used to form various features and multiple levels or layers of semiconductor devices on a surface of a semiconductor wafer or another appropriate substrate.
Physical (PVD) and chemical (CVD) vapor deposition methods, and also the deposition of conductive coatings through various decomposition processes of gaseous, liquid or solid precursors may be used in the formation of semiconductor devices.
Additionally, lithography is a process used in the formation of semiconductor devices that typically involves transferring a pattern to a resist arranged on a surface of a semiconductor wafer. Lithography is commonly used to define small-scale features of semiconductor devices and often sets a limit on the goal of device miniaturization.
Additional examples of semiconductor fabrication processes include chemical-mechanical polishing, etching, deposition, ion implantation, plating, and cleaning. Semiconductor devices are significantly smaller than a typical semiconductor wafer or substrate, and an array of semiconductor devices may be formed on a semiconductor wafer. After processing is complete, the semiconductor wafer may be separated into individual semiconductor devices.
In semiconductor device fabrication, it is desirable to reduce the length scale or feature size of devices as much as possible so that a larger number of devices can be formed on a given substrate area. As the feature size of devices is minimized, however, processing of the devices becomes more difficult. Small scale features become more difficult to define as the lithographic limit of resolution is reached and features that are defined become more difficult to process.
A common step in processing involves depositing a layer and forming an opening in it. Openings such as channels, trenches, holes, vias, pores or depressions in layers are commonly employed to permit interconnections between devices or layers of a structure. Typically, the opening is formed by lithography or etching and is subsequently filled with another material. As the dimension or length scale of an opening decreases upon miniaturization, it becomes increasingly difficult to satisfactorily fill the opening with another material.
Techniques such as physical vapor deposition (PVD) or sputtering fail to provide dense or complete filling of openings when the dimensions of the opening are reduced below a critical size. Instead of providing a dense, uniform filling, these techniques increasingly incompletely fill openings as the dimension of the opening decreases while the depth stays the same, thus increasing the aspect ratio. The deposited layer of material includes gaps, pores, or other unfilled regions. The packing density of material formed in the opening may vary in the depth or lateral dimensions of the opening.
Lack of structural uniformity in the filling of openings compromises device functionality as variations occur from device-to-device across an array of devices on a substrate. In addition, less than optimal performance is achieved for each device due to the defective nature of the deposited material. Imperfections in filling openings become especially pronounced as the aspect ratio (ratio of the dimension normal to the substrate to the dimension parallel to the substrate) of the opening increases. Deep, narrow channels, for example, are more difficult to uniformly fill than channels that are shallow and wide. With deep, narrow features, sputtering and other physical deposition techniques are oftentimes unable to deliver sufficient material to the bottom of the feature. Instead, a layer of material is formed over or only near the top of the feature and the lower part of the feature is blocked and remains largely unfilled.
Conformality of deposition is another processing difficulty that becomes exacerbated as feature size decreases. Fabrication of semiconductor devices generally involves forming a stack of layers, where the individual layers may differ in dimensions (lateral to or normal to the substrate) and compositions. The process of fabricating a semiconductor device generally involves sequential deposition of one layer upon a lower (previously formed) layer. Optimal device performance requires conformality of later formed layers with earlier formed layers. Each layer in a stack must conform to the shape and contours of the layer in the stack upon which it is formed. Smooth and uniform coverage is desired.
In addition to difficulties with achieving uniform filling, openings also present complications for achieving conformal deposition that become more pronounced as size of the opening decreases. The boundary or perimeter of an opening is frequently defined by an edge, step, or other relatively discontinuous feature. The shape of an opening is generally defined by a sidewall or perimeter boundary and a lower surface or bottom boundary. A trench opening, for example, is defined by generally vertical sidewalls and a bottom surface that is generally parallel to the substrate.
When fabricating semiconductor devices, it is often necessary to first form a layer with an opening and to subsequently deposit another layer over this layer. Conformality requires that the subsequent layer faithfully conform to the shape and texture of the underlying layer having the opening. The subsequent layer must deposit uniformly over both the portion of the underlying layer in which the opening has not been formed as well as over the opening itself. Conformality over the opening requires uniform coverage of the edges or steps that form the boundary of the opening. Achieving conformality over discontinuous features becomes increasingly difficult as the feature size of the opening decreases or the aspect ratio of the opening increases.
Fabrication of programmable resistance and switching devices often includes a step of forming an opening in a dielectric layer and filling the opening with a conductive material to form an electrical contact. Miniaturization of programmable resistance and switching devices requires methods for reducing the dimensions of the electrical contacts. Contacts with small dimensions are beneficial because the energy required to operate programmable resistance and switching devices decreases with decreasing contact size. Accordingly, it is desirable to develop techniques for forming and filling openings with small dimensions without suffering from the imperfections in filling and conformality associated with standard prior art techniques such as sputtering or physical vapor deposition. Ideally, the techniques would enable the fabrication of electrical contacts for programmable resistance and switching devices having dimensions near, at or below the lithographic limit.
Referring to the drawings, FIG. 1 depicts a representative structure of a phase change material device that illustrates the nature of imperfections that may form in an electrical contact having a sublithographic dimension when the contact is deposited via sputtering or physical vapor deposition. A conductive layer 106 is formed over a substrate 102. An insulative layer 110 having an opening formed therein is then formed over conductive layer 106. Lower electrical contact 128 is formed in the opening of insulative layer 110 using a sputtering or physical vapor deposition process. A layer of phase change material 114 is then deposited onto lower electrical contact 128 and a top electrode layer 116 is deposited over the phase change layer 114. Lower electrical contact 128 includes imperfections in the form of internal voids 120 and non-conformal region 112. The imperfections detract from device performance. The prevalence of the imperfections increases as aspect ratio of the opening increases.
Chemical Vapor Deposition (CVD) is one method available in the prior art for filling openings that is expected to remain effective as the feature size of the opening decreases. The molecular dimensions of the gas phase precursors used in CVD allow the precursors to enter small dimensional openings, where they subsequently react to form a relatively uniform layer. Although CVD in principle is a viable strategy for forming lithographic or sublithographic contacts in programmable resistance and switching devices, the technique is limited in practice because of the unavailability of gas phase precursors for a variety of desirable contact materials. In addition, the reaction conditions (e.g. high temperatures or plasma conditions) needed to react the precursors may damage other layers in the device structure. There is a need, therefore, for alternative methods of forming electrical contacts in openings having small dimensions.
To address these issues, chemical solution-based conformal deposition may be used to reduce structural irregularities in photolithographic and subphotolithographic structures, and to selectively fill openings with one or more desired materials thereby increasing the design flexibility and quality of the resulting devices.